Researchers have conducted a comprehensive review of using Large Language Models (LLMs) for generating Verilog code. The study analyzed 102 papers and identified limitations in existing research. It found that various LLMs are being used for this task, but there is no standard evaluation metric or dataset. The authors propose a roadmap for future research to improve the effectiveness of LLM-assisted hardware design. They aim to address four key questions: which LLMs are suitable for Verilog generation, what datasets and metrics should be used, how can techniques be categorized, and how can LLM alignment approaches be analyzed. --- Why it matters: This review matters because it provides a systematic analysis of the current state of research on using LLMs for Verilog code generation. Its findings will help researchers identify areas for improvement and provide guidance on future directions for advancing automated hardware design. Source: https://arxiv.org/abs/2512.00020